1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof. More particularly, the present invention relates to a semiconductor device having a lower parasitic capacitance and a manufacturing method thereof.
2. Description of Related Art
Along with the advancement of the semiconductor technology, device dimension continues to decrease. As semiconductor devices enter the deep sub-micron processing and integration of integrated circuits increases, the wafer surface is insufficient to provide enough space for the fabrication of the required interconnects. In order to accommodate the increase of interconnects due to a diminution of the device dimension, the multi-layer metal interconnects design with two layers or more is the technique used in the Very Large Scale Integrated (VLSI) circuits.
However, during the complicated interconnection design of a multi-layer interconnect, parasitic capacitance is often generated in a structure having a dielectric layer sandwiched between two conductive structures. For example, in a memory device, after forming the gate structure, a dielectric layer is normally formed to cover the gate structure, followed by forming a bit line on the dielectric layer. As a result, parasitic capacitance is generated due to the bit-line coupling effect between the bit line and the gate structure.
The presence of the above parasitic capacitance would result in signal noise, adversely affecting the effectiveness of the device. To mitigate the parasitic capacitance in integrated circuits is an imminent problem needs to be readily resolved.